1. Field of Invention
The present invention relates to a flash memory cell and fabricating method thereof, and more particularly, to a flash memory cell for tunneling electrons stored in a floating gate with an erasing gate, and a method of fabricating of the same.
2. Discussion of the Related Art
A flash memory cell is an inactive memory device having a floating gate and a control gate, the control gate being positioned over the floating gate. The memory cells of an array of flash memory cells are erased simultaneously and the speed of erasing is extremely fast.
To program a flash memory cell, hot-electrons are injected into the channel by applying high voltage to the control gate and into the floating gate. A coupling ratio is defined by, the voltage applied to the floating gate over the other voltage applied to the control gate. The more the coupling ratio increases, the more efficient the program becomes.
The flash memory, cell is erased by injecting the electrons of the floating gate into the source region of the semiconductor substrate to which high voltage is applied according to the tunneling mechanism of Fowler-Nordheim. Moreover, the erasing operation can be achieved by tunneling the electrons stored in the floating gate into the erasing gate with an extra floating gate.
The thickness of the portion of the gate insulating film lying under the floating gate is decreased to improve the efficiency of the erasing operation. The decreased thickness of the film effectively lowers the voltage applied to the floating gate due to the decreased coupling ratio. Hence, the efficiency of the erasing operation for the programming is increased while the coupling ratio is maintained.
FIG. 1 shows a cross-sectional view of a conventional flash memory cell. To fabricate the flash memory cell of FIG. 1, a floating gate 15 is formed having a gate insulating layer 13 underneath. To form the floating gate 15, a polycrystalline layer doped with impurities is patterned. After forming floating gate 15, a control gate 19 is formed on floating gate 15, a second gate insulating layer 17 being formed therebetween, wherein the control gate 19 is defined to have a striped pattern that is crossed by the direction of channel length. Thereafter, a sidewall spacer 25 is formed at the lateral surface of the first gate insulating layer 13, the floating gate 15, the second gate insulating layer 17 and the control gate 19.
A source region 27 and a drain region 29, which are doped heavily with N-type impurities, are then formed in the substrate 11 under both sides of the floating gate 15. A lightly doped region 23 with an N-type impurity is formed immediately below the source region 27 in the semiconductor substrate 11. The
First, a gate voltage Vg of 12 V is applied to the control gate 19, a drain voltage Vd of 5 to 6 V is applied to the drain region 29 while the source region 27 is grounded. Thus, a channel is formed under the floating gate 15 in the semiconductor substrate 11 by the gate voltage Vg which has been applied to the control gate 19, and electrons accelerated by the drain voltage Vd applied to the drain region 29 are injected into the floating gate 15 over the energy barrier of the first gate insulating layer 13. Since the threshold voltage of the cell has increased based on the injection of electrons into the floating gate 15, programming is completed.
However, when operated in this manner, the efficiency of the programming depends on the value of the voltage induced from the gate voltage Vg which has been applied to the control gate 19. Namely, the larger the coupling ratio determined by the voltage induced to the floating gate 15 over the gate voltage Vg applied to the control gate 19, the more efficient the programming becomes. The coupling ratio increases provided the capacitance of the first gate insulating layer 13 is relatively small or the capacitance of the second gate insulating layer 17 is relatively large. Hence the second insulating layer 17 is formed with a structure of Oxe2x80x94Nxe2x80x94O(oxide-nitride-oxide) layer to increase its capacitance.
In order to erase data programmed in the flash memory cell, the electrons in the floating gate 15 are tunneled into the heavily-doped source region 27 by applying a source voltage Vs of greater than 15 V to the lightly-doped source region 23 while the control gate 19 is grounded or provided with negative voltage. The electrons migrate from the floating gate 15 to the source region 27 through the first gate insulating layer 13 based on Fowler-Nordheim tunneling, thereby lowering the threshold voltage of the cell and erasing the cell. In addition, the lightly-doped source region 23 prevents the application of high voltages to the heavily doped source region 27 during junction breakdown since it diffuses the junction deeply. The first gate insulating layer 13 is formed thinly in order to improve the efficiency for erasing the cell since the electrons migrate from the floating gate 15 to the heavily doped source region 27 through the first gate insulating layer 13.
FIGS. 2A to 2D show a cross-sectional view of steps in the process of fabricating the above-described flash memory cell according to the prior art.
Referring to FIG. 2A, a first gate insulating layer 13 is formed by thermal oxidation of the surface of a P-type semiconductor substrate 11. A polycrystalline silicon layer doped with impurity is deposited on the first gate insulating layer 13 with CVD (Chemical Vapor Deposition). A floating gate 15, which has a striped pattern in a first direction determined by the channel length, is formed by patterning the polycrystalline silicon layer via photolithography.
Referring to FIG. 2B, a second gate insulating layer 17 comprising oxide-nitride-oxide is formed to cover the floating gate 15. A control gate 19 is then formed on the second gate insulating layer 17 by depositing polycrystalline silicon doped with an impurity by CVD.
Referring to FIG. 2C, the control gate 19, the second gate insulating layer 17, the floating gate 15 and the first gate insulating layer 13 are sequentially patterned, via photolithography, in a second direction defined perpendicular to the first direction. A photoresist pattern 21 exposing a certain part of the semiconductor substrate 11 is then defined, and a lightly-doped region 23 is formed by implanting an N-type impurity into the exposed part of the semiconductor substrate 11. The exposed part of the substrate 11, into which regions 23 is formed, is not protected by the photoresist pattern 21 which acts as a mask. The edge of the lightly-doped region 23 overlaps part of the floating gate 15 due to diffusion and the like.
Referring to FIG. 2D, the photoresist pattern 21 is removed, and an oxide is deposited on the semiconductor substrate 11 with CVD to cover the control gate 19. Then, a sidewall spacer 25 is formed at the lateral surfaces of the first gate insulating layer 13, the floating gate 15, the second insulating layer 17 and the control gate 19. Using the control gate 19 and the sidewall spacer 25 as a mask, a source region 27 and a drain region 29 are formed by implanting large amounts of an N-type impurity into the semiconductor substrate 11, wherein the source region 27 is positioned over the lightly-doped region 23.
However, through this process, the efficiency of the programming decreases due to the decline of the coupling ratio since the capacity of the first gate insulating layer is enhanced by its thin construction, a construction that is used by the conventional system to improve the erasing efficiency.
Additionally, the reliability of the conventional flash memory cell is poor since the data programmed in the floating gate may be erased by the drain voltage, and the construction is complicated since it is difficult to form the first. insulating layer thinly. Moreover, the dimensions of the device increases and the process becomes further complicated in an erasing operation since the lightly-doped region 23 is necessary for preventing the destruction of the source junction from the high voltage applied to the source region.
An object of the present invention is to provide a flash memory cell and fabricating method thereof that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
It is an object of the prevent invention to provide a flash memory cell which improves efficiency of programming by increasing the coupling ratio while preventing a decline in the efficiency of the erasing operation.
Another object of the present invention is to provide flash memory cell having reduced dimensions.
Another objection of the present invention is to provide a method of fabricating a flash memory cell based on less steps for fabricating, and a flash memory cell that is formed without an extra region to prevent the source junction from destruction.
A further object of the present invention is to simplify the method of fabricating a flash memory cell by forming a thick first gate insulating layer.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes a semiconductor substrate having a first type impurity, a first gate insulating layer on a first certain part of the semiconductor substrate, a buried insulating layer on a second certain part of the semiconductor substrate, the buried insulating layer being connected to the first gate insulating layer, a floating gate on the first gate insulating layer wherein the floating gate extends on and is overlapped with the buried insulating layer in part, a second gate insulating layer on the floating gate, a third gate. insulating layer at a lateral surface of the floating gate, a control gate on the second gate insulating layer wherein one side of the control gate corresponds to that of the floating gate and the other side of the control gate does not correspond to that of the control gate and the one side of said control gate overlaps over the buried insulating layer, a fourth gate insulating layer on the control gate, an insulating sidewall spacer at a lateral surface of the control gate and a lateral surface of the fourth gate insulating layer wherein the insulating sidewall spacer lies over the buried insulating layer, an erasing gate on the buried insulating layer wherein the erasing gate is separated electrically from the floating gate and said control gate by the third gate insulating layer the insulating sidewall spacer the fourth gate insulating layer, and a source region under both buried insulating layer and one side of the floating gate wherein the source region has a second type impurity.
The above-explained structure does not require a lightly-doped region which prevents the breakdown of the source junction, decreasing the bulk of a device.
In another aspect of the present invention, a method of fabricating flash memory cell includes the steps of implanting a second type impurity heavily into a certain part of a semiconductor substrate of a first type impurity, forming both a first gate insulating layer and a buried insulating layer by means of oxidizing a surface of the semiconductor substrate including the certain part, forming a source region by means of diffusing the second type impurity during the oxidizing process, forming a floating gate on the gate insulating layer to a first direction wherein the floating gate has a striped pattern, forming a second gate insulating layer on a certain portion of the floating gate wherein the second gate insulating layer has a striped pattern to a second direction perpendicular to the. floating gate, forming a control gate on the second gate insulating layer, forming a capping insulating layer on the control gate, forming an insulating sidewall spacer at lateral surfaces of the second insulating layer/the control gate/the capping insulating layer wherein the lateral surfaces lies over to the buried insulating layer, patterning the first gate insulating layer and the control gate in use of the capping insulating layer and the insulating sidewall spacer, forming a third gate insulating layer at a lateral surface of the floating gate, forming a drain region in a disclosed part of the semiconductor substrate wherein the drain region has a second type impurity, and forming an erasing gate over the buried insulating layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.